I have a PCB design with 3 copper zones on separate layers and an unmasking pour on the front mask.
Since adding the pours to a net they no longer fill. I have a via between two of the zones that are the same net but nothing. I need to do via stitching and this will not work if the zones are not poured.
Yes, but the whole business of PCB design is based on restrictions put on design elements. They are there to help you. There are good reasons why zones behave that way. If you want something else, you are using a wrong tool.
I decide the board I want to design. I would have thought the software would have tools that enable me to create what is possible. A layer of copper with just the way I want it is possible. My zone in this case is chassis ground and a bit of a shield. Nothing at all from a manufacturing perspective is a problem here. The problem is the software will not let me create what is possible.
If the zone has no net it should fill in any case. If it’s GND or something comparable it should be tied to some pad of that net anyways and is filled as you wish. If it doesn’t need to “avoid” any items (go around pads but not touch them) but is just a filled polygon, a graphic polygon does the job. There are many ways to skin the cat. Just don’t blame KiCad if it works as it should.
My guess it your use case is uncommon enough has it’s not been considered to add such an option.
In your case I would make a SMD component (say a resistor) with a custom footprint to jump your isolated plane to some other net. I realize this will leave you with two pads but you can make the custom footprint have really small pads.
Why not? If I have a copper zone I can choose what to do with the unconnected bits, there is an option to fill unconnected bits which I do having eliminated all the ones I can as it seems fabs don’t like too much bare board anyway. I sent a design to one fab and it had no planes at all as it was a really simple board. They contacted me and asked if it was OK to fill the board with an unconnected plane and here you are telling me that what newbury electronics / PCB train requested as a board manufacturer is “wrong”.
Why is it against some rule? If I do want suk an area what do I do? I have a valid reason to be doing what I am doing and it is totally possible to manufacture it, are you saying that KiCad knows more about what I need than I do?
Unconnected copper (especially large zones) negatively impact EMC behavior.
If you want unconnected to be filled in version 5 then add a zone that has no net assigned (this is what @eelik meant, you misunderstood the sentence you quoted from him -> he gave you the solution not a reasoning as to why not to do it).
The current nightly (so later on version 6) however might already have a option for zones to allow filling of unconnected bits but i am not sure how this exactly behaves.
Again, you and KiCad do not know my design and if KiCad is supposed to know more about EMC in my design than me then the developers are very much mistaken! The reason I am trying to do this is for EMC. I have a circuit that goes into a custom enclosure and will sit on that enclosure so that 5 sides of the box are in the enclosure metalwork. My PCB is the 6th side. The Back of the PCB shall be chassis and as such does not require any components or nets for that matter. I am trying to create on one side a ring of exposed copper for shielding gaskets to sit on and through via’s to the bottom layer will be connected forming a full shield around the circuit. But, KiCad apparently knows more than I do about what I need.
I am still to hear a real valid reason why KiCad has this behavior. It is obstructing my design and unless KiCad is going to do the design for me like some futuristic AI I suggest it does it’s job and let’s me do mine.
Polygons are not suitable as they won’t have the properties of zone that will adapt to board edges. I also have to move a polygon from the user drawing layer where it insists on going no matter what layer I was on.
I’m willing to make the problem understood and to help. It’s possible that we don’t still understand the situation well enough.
Of course KiCad doesn’t know about EMC and doesn’t try to inhibit such problems. But it acts in a certain way because the users mostly need certain kind of behavior. That’s pretty usual for computer programs AFAIK. For rarer situation there are other ways to achieve what you want.
If I understood your explanation correctly you have a separate GND (or whatever) net in your circuit but this chassis circuit isn’t connected to it. Right or wrong? If wrong, and it’s connected to GND, you should connect it to some GND pad in some way. If right, there are a couple of ways to achieve what you want. I mentioned them earlier.
If you tell I was right, we can continue explaining why KiCad acts that way. It doesn’t want to bully you. It’s just that separate zones belonging to some net without pads aren’t meant for that. I’m not sure why you think KiCad should read your mind and change the behavior when you want to do something in a wrong way. If it did that always automatically, it would produce broken designs for others.
Yes, you have to change the layer manually to a copper layer because mostly polygons (which don’t have nets) are potentially dangerous and need extra manual care. All the time, KiCad tries to enable the most common use cases easily. With copper layers restrictions are necessary; otherwise people would have broken designs and would ask “why didn’t KiCad prevent that in the first place”.
My power ground and device chassis are separate, The metal enclosure is not part of the circuit. There is of course a power ground. The layers I described are effectively part of the enclosure so have no nets and no need for tracks but I do need them stitched with via’s. However the copper features I want to create are nothing exotic, they just don’t need a net.
Having added some suppression capacitors from GND to chassis I have nets and tracks, it was a good idea to add them but I was forced to, to make the zones pour.
I don’t want KiCad to think for me, but it appears that it is thinking for me at the moment. I don’t see how as a board manufacture what I want is no good, it is a reasonable thing that can (should) be easy to design and a fab would have no problem making. Why is KiCad deciding what copper I can and can’t have?
It seems to me that you just don’t know how to use KiCad correctly for this use case.
Maybe you should add a mounting hole symbol with pin to the schematic (I think you have a mounting hole, “ring of exposed copper”, through which the board is connected to the chassis, right?). It will have a net. Then attach the mounting hole footprint for it. Update the board from the schematic. Then add the zone to the net and make it surround the mounting hole. It should fill. Add capacitors between the nets in the schematic/board.
KiCad knows only what you let it to know. It didn’t know about any external net (the chassis) because you didn’t tell it. KiCad can’t guess what the user wants if it doesn’t have enough information.
You assume wrong. The zone needs a net because it’s part of the design. If you don’t want a net for it, then do it manually with polygons or something. KiCad works logically here, you’re not accustomed to its logic. Cool down and accept that KiCad didn’t read your mind.