I think the problem is that we have no proper assembly layer in libraries. Putting too small references on silkscreen is wrong but the references scaled to footprint should actually be put on assembly layer.
I’ve been wondering about this. For now I’ve followed KiCads lead and moved the values and similar stuff to the front fabrication layer, but I’m not entirely convinced that’s the way to go. But it is an improvement over the old footprint conventions.
I will ask on mailing list.
I think it is great that you decided to create better footprints and share them with the community. That is what free software is all about! 
This post raised my curiosity and I had a look into the IPC-7351. For what I can see there are two methods of creating a “IPC compliant footprint”. The first includes all dimensions and tolerances of the part and based on that calculates an ideal footprint. The second method is more straight forward and just takes the nominal dimensions and based on a reference table for the class of component you have you add a margin for “heel, toe, side” to create your footprint. For both methods there is a density class A/B/C that allows easier soldering or more dense component placement.
This made me wonder if there actually is such a thing as a IPC compliant footprint for standard components? I checked a set of 0805 (2012 metric) resistors from different manufacturers and looked up their dimensions. All had external dimensions L=2.00mm x W=1.25mm nominal, but tolerances varied from +/- 0.10 to +/- 0.20 mm. The width of the terminal does not seem standardized and varied between 0.30 and 0.40 mm. The differences are minor but their IPC compliant footprints will vary with the same amount; i.e. without standard component dimensions and tolerances, how can there be an IPC compliant footprint? Is there a standard on which these footprints should be based?
Yes - IPC-7351
Normally you would use the same IPC calculator referenced above and calculate you footprints based on dimensions, tolerances and weither you want it to be min, nominal or maximum. The calculator would automatically generate the footprints. Unfortunately, although predictably, it doesn’t output footprints in kicad format. That’s the only way to do it correctly. Although if you make a library of nominal footprint ( not the ones we have in the cap library though) they will work for most cases. I didn’t see such variations in base dimensions of chip components between manufacturers. What manufacturers did you look at? It is not AVX per chance? 
I went to digikey and looked at all 0805 components available. Max variation in width was 0.1mm and length 0.19mm
Thanks for your reply. To elaborate a bit more, let’s consider the following two 0805 resistors:
Vishay CHPHT High Temperature (245 °C) Thick Film Chip Resistor
L = 1.85 mm
W = 1.25 mm
S = 0.50 mm
TT Electronics Precision Thin Film Resistor
L = 2.06 mm
W = 1.27 mm
S = 0.41 mm
Both resistors are 0805 and I assume it should be OK to have a single footprint for both of them (they should both comply to the “0805 standard”). The question is how should I dimension this ‘universal’ 0805 footprint?
There is no universal 0805. IPC-7351 provides method of calculation. I don’t know if it provides also standard 0805 package dimensions (maybe in some different document?), I know that EIA 198 defines some standard packages dimensions [1], but manufacturers can follow different standards or break them. To be sure that footprint is correct one should calculate footprint for every part he wants to use or follow recommendations from its datasheet.
[1] http://www.kemet.com/Lists/TechnicalArticles/Attachments/29/f2100e.pdf
That is not exactly correct. You can make a footprint that would be made to the max dimension with max tolerances and lowest density class and it will accommodate any commercially available resistor of that particular form factor … and that would be the worst thing you can possibly do. The goal should be quite opposite - to minimize the size of the footprint.
Let me back up a little. As I mentioned before there are two ways of going about it. Calculate footprints for each component, which would be truly compliant with the IPC standard. That approach would not really work for KiCad because nothing out there really support KiCad footprint format and trying to convert it back and forth from other formats would become old really fast. If KiCad in the future simplify working with the libraries (so you would not have to muck about finding and opening a library first and then finding and opening a footprint within that libarary) and make it possible directly opening say Eagle or Altium files it can become an option.
The second option is to have nominal footprint library and that the option currently used by KiCad and it works just fine (with the exception that the logic behind organization of the libraries is somewhat lacking and some dimensions are not exactly “nominal”) Yes it is possible find a components out there that might be slightly constrained for space on this nominal footprint, but it will still work and populate with very little effort during manufacturing. It really is not rocket science. You just need to have a library of components that is more or less in the middle and correlate with the majority of components.
I suggest you look at the IPC calculator and play around with all the values. Here are the values I’ve got for the two resistors you’ve got there (with designations being L - Total length of the pad, W - total width of the pad, S - gap between two pads)
Vishay L - 1.06 W - 1.4 S - 0.6
TT L - 1.00 W - 1.42 S - 0.92
If you compare the outside dimensions for both footprints they are very close so you can come up with the footprint that will work for pretty much all of them. Now if you look at the manufacturer suggested footprint for Vishay (TT doesn’t offer one) the values are: L - 1.13, W - 1.38, S - 0.44 . Originally, I didn’t convert them to the same convention, so I thought those were way off, but as you see, those are pretty close still. The gap between the pads is slightly smaller and total pad length is slightly bigger, but Vishay specifies the total length as maximum dimension and gap as minimum. So technically any of the calculated values above fall into the “manufacturer recommended” range for the footprint.
Dear ArtG,
The IPC is a club that has to satisfy every member, and as an organization it is rather slow.
Therefore the footprint calculator has a “better-safe-than-sorry” approach towards dimensions: if you send off your design to a random IPC member you can be sure it will be manufacturablke.
However, a lot of PCB makers are able to make PCN’s with much tighter tolerances, have better than average pick and place machines etc.
So for us is it profitable to adjust the footprints to save boardspace and align them in a way our PCB maker can still mount the components. The IPC standard footprint is overkill in boardspace.
We make a custom footprint for every component we use, in collaboration with our PCB maker, and it pays off.
So IMHO “universal footprints” are only useful for distributing open source lay-outs etc. where one should be able to send the the design to any random PCB maker.
My two cents worth,
Loek
P.S. We have special footprints, and extra room around to work with, for components that are anticipated to patch by hand.
You have freedom to make any footprint you think is appropriate. However that doesn’t mean that everybody should adopt the same ideology. IPC represents a reasonable base line. IPC also covers three density classes. You can probably find a manufacturer that can shoot chips with 0.005" spacing but why? If your time that you spend messing with footprints worth nothing, at least you should think about manufacturability and cost associated with it. In a crowded board you can always go with smaller chip component footprint.
But that is all besides the point. That’s not the subject of this thread.