Board outline does not form a closed polygon (adjacent polygons)

Usually that layer is Edge.Cuts, and the convention is that interior edge to edge lines in that layer are V-cuts, not board outline. Wouldn’t hurt to ask the fab and also mention it in a note. Source: I have done this a couple of times after checking with the fabs.

Ocean Smile: https://www.cnospcb.com/support/what-are-the-v-cut-panelization-rules.html

JLCPCB: V-cut and rounded corners (an old thread I started)

Here’s one I did of panelised breakout boards. The 3D viewer complained but still rendered the board, minus the V-cuts.

Incidentally it’s not true that you have to consult them about the size for “alignment” or “wastage” reasons. They don’t have any restriction on what size you create within the 100x100 mm envelope (which comes from an old Eagle restriction for free use) for cheap boards (or larger boards, if you pay more). They may however slap you with an “engineering charge”, which is to compensate for the extra effort to run the boards through the V-cut machine. I got charged a bit more for the example above for the 7 V-cuts, but the board was a freebie anyway.

Panelisation works at two levels. At the fab level they have engineers or technicians solving the 2D knapsack problem every day packing boards of different sizes and aspect ratios on their large panels. To fill the “wasted space”, they offer cheap PCB fabrication under 100x100 mm in quantities of 5 or 10. Your design is photographically combined with those more important orders in a exposure mask. So your 5 or 10 boards are actually coming from 5 or 10 distinct large panels. Cheapskates like me then try to squeeze in more tiny boards by doing our own panelisation. The fabs tolerate this to some extent if it doesn’t cost much more, until they decide you should pay a bit more.

This is also why your small board may be delayed a little bit until they can fit you in. For high volume fabs the wait will be shorter.

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