Hello
i am drawing a proto shield
I have drawn tracks to connect i have watched there is a problem.
The problem is : track near pad.
What rules should i change to remove this error?
None at this point. 
Can you either share your design or at least a picture of the area that is causing problems?
EDIT: Do you have ‘allow drc viloations’ set in your routing preferences?
The problem is about the tracks that pass between the drills.
Thanks.
PCBNew>preferences>interactive routing
I don’t know this will allow you to pass checks. If unchecked it should let you know when routing that a problem exits.
If you are sure there isn’t a problem don’t get too hung up on this. I used a library footprint for a to-220 package that violated the DRC checks. It had larger pads for hand soldering. The software should indicate where the problem is so you can check, and if proper, dismiss the flag.
I have only ever changed the track clearance and width under design rules. If you set the clearance to what your board maker allows you should be good to go.
I have used PCBNew> preferences> interactive routing but the problem is the same.
I have watched that when i delete a part of a track i can’ t redraw this part (i can not connect).
The default clearance is 0,2 and the other one is 0,1524
The default clearance settings in pcb new are very conservative. (Most manufacturers can produce boards with smaller clearances.)
You now need to decide which manufacturer you will use to produce your pcb. Every manufacturer has a document describing their capabilities. (min trace width, min clearance, …)
You need to setup the DRC rules and clearance settings according to these manufacturer requirements.
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I use Kicad and i have choosen Seeedstudio as manufacturer.
I think it can be a problem concerning the net list because it says me “Error cannot new component due to missing footprint”.
I can not make any track between the female headers and the other holes on the protoshield that i would like to connect to the female headers.
The missing footprint message gives you a reference designator. Check this component in eeschema. (Answer the following questions.)
- Is a footprint assigned?
- If you have assigned a footprint, is it valid (Does this footprint even exist?)
- If you are using online footprint libs, you need access to the internet while importing footprints. If this is not guaranteed i would suggest you switch to a local footprint lib setup. (follow this tutorial for a local setup. This tutorial is written by @bobc.)
What are your DRC settings? (Track width, clearances, …)
What is the distance between the pads of your connector?
A track can only be layed between pins if you have space for two times the clearance plus your track width.
If your manufacturers capabilities are not good enough to get a trace in there either select a different connector or a different manufacturer. (Or a more expensive version at your manufacturer.)
Another option is that the footprint is simply designed wrong.
(Pad size too large -> too little space between the pads.)
If it is a THT header make sure you do not reduce the pad size such that you are below the minimum required annular ring of your manufacturer. (This is not checked by DRC but there are scripts out there that can check it.)
And remember the smaller the pad the harder it gets to solder it. (And the current capacity goes down as well.)
If you give us more details about your connector then we might be able to check a few things.
You seem like a beginner that jumped into the deep end.
Did you already go through some tutorials? (Example getting to blinky 4.0)
You could also read some of the tutorials by sparkfun.
And example: https://learn.sparkfun.com/tutorials/pcb-basics (Explains basic terminologies, gives links for further reading at the end.)
Spark fun also has a tutorial section dedicated to kicad: https://learn.sparkfun.com/tutorials/beginners-guide-to-kicad
It might be more efficient if you somehow get a “teacher” who you can meet in person. Here a few suggestions on how to find one:
If you have a hobby electronics club near by maybe talk to them. (Hackerspace, Fablab, …)
They might be able to teach you some stuff.
Are there linux days or other open source related workshops near you? Do they offer courses on kicad/pcb design?
If you are a student. Is there a student team at your university (Formula Student, Eco racing, robocup, …) They should know how to design PCBs. (They might share their knowledge if you help out with other tasks.) Does the electronics faculty offer courses on PCB design?
Thank you for the advice.
I’m a fan of electronics and, in my spare time, I try to learn new things.
I have no one who can help me near me and I try to learn by myself.
I asked for help in this forum for this reason.
Then you need to help us help you. (More details required.)
It might even be a good idea to split it up into different topics. (Even though some of them might share a common root cause. The header connection and your problems with understanding DRC might be related. But there could also be a different problem.)
I think you might already have at least 3 different questions here. Possible titles would be:
(Remember most users only read the title.)
- Can someone explain the meaning of the design rule check and how i translate manufacturer requirements to kicad?
- Here it might be a good idea to tell others what manufacturer you intent to use. (you can even give the link that you got above.)
- Having problems connecting traces to a pin header.
- You need to give details about what header you intent to use. (Link to a datasheet.)
- Maybe share your footprint. (If it is in the default kicad lib you can tell us it’s name otherwise you need to attach it.)
- A screenshot holding the problematic area might also be a good idea.
- Problem with importing netlist. I get an error message about missing footprint(s).
- Again more details needed. (What is the exact error message. What footprint did you assign to the affected component.)
Is future or current PcbNew allows user to save a library of DRC settings per manufacture/process? And potentially share just like fp libs, or symbol libs ?
Already possible using templates. Later import is not possible right now.
Are these setting come from the XYZ.kicad_pcb file from template? This mean, one can make a short python script to swap the setting if the syntax in the kicad_pcd isn’t too complex. Or if the script feature allow to access these setting, then it may be nice for all kind of 3rd-party plugin to play with…
Pretty much, yes. Actually, something I’ve been thinking about but never seem to find the time to actually start on it is a python action script to do this. Just because the board house you plan on using claims that they are capable of (for example) 6mil traces (0.1524mm), doesn’t mean that they have a 100% reliability at that small size. Unless you pay extra for them to do board testing, you as the customer will eat the cost and time of unusable boards. So it is a general good practice to specify your design minimums slightly larger than the manufacturer’s capabilities. My thoughts for this as-yet unwritten script is to have a standardized ASCII file format for what the manufacturers specs are. The script would allow the user to select the mfg standards file and then compare the board geometry to the standards in the file. This would also check items that PCBNew doesn’t (currently) check for, like minimum annular ring. Would probably steal liberally from this thread for annular ring checking: Annular checking: How do I check if all my pads diameter is drill diameter +0.3 (or so)?
This way one could verify that your used minimums are compatible with different vendors.
If anyone else wants to run with this idea, feel free.
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For the ACSII file format, I think we can just use the same exact syntax in the .kicad_pcb (part for the DRC setting). So coding for supporting it is minimum… Event for temporary, we can have multiple .kicad_pcb for difference manufacture, and have the script just read and overwrite the DRC setting areas in the .kicad_pcb file… Just a though…