In theory, no. In reality, sometimes. Like I said. Sometimes I just ended up redrawing them without ever understanding what didn’t work because that was the course of least resistance.
Redrawing the entire pcb? Ive tried a new project and also just redrawing the square to be filled to no avail. I did upgrade it to 4.07 and tried it upon your suggestion. Didnt make a difference so far.
No. Just redrawing the fill zone always worked for me when I had trouble. I see by the first screen you are a Windows user. Shouldn’t make a difference but I’m a Linux user.
Ah i see. I did try redrawing the fill zone multiple times. I will try F9 and F11 thing and get back to you. Thanks for your suggestion
As a note, this question is also posted with more detail at SE (https://electronics.stackexchange.com/questions/394057/add-filled-zones-doesnt-work).
You need to have your zone on the same layer as your signal. It’s not visible in this image but all of your components are on F.Cu. If you want the fill to work, it’ll need to be on the same layer.
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I see. So my filled zone has to be also on F.Cu. Sorry my deadline is approaching fast. Ill take the exchange post down if its violating the rules.
No worries, as long as you get it resolved. 
Just noted here to allow others to view the extra images that explain the problem.
Thank you. Since im out of my office at the moment, im trying to gather as many suggestions as possible.
We had this issue when the filled zones were not big enough. The pad clearance area and the board outline then suppresses the zones. Maybe this is here also the problem.
Is this a student project that you need to turn in?
Or is it a small project that will go in production?
If it is the former then is assume your professor has defined that there needs to be a copper zone and that is why you add one. (Without thinking as to why it would make sense.)
Having a copper zone on the back side is normally done for a reason. In most cases because you want better ground connections for EMC/EMI reasons. (With better i mean low impedance)
In your case it looks like there are no connections missing that the copper zone could possibly take care of.
KiCad only fills zones (that have a net assigned) if they are connected to a pad in one way or another. This can happen by using a trace, a via or the zone is in direct contact with the pad.
More details can be found here: Filled Copper Zones not showing up in Gerbers/Printouts/3D view
(No, it’s not homework per se, I just needed to implement an existing circuit design for my ongoing experiment for data acquisition)
Thanks to everyone’s input, I was able to design the pcb in the image below.
If there are any design improvement suggestions you guys could offer, or any mistakes that DRC wouldn’t catch, I would appreciate it.
To be picky, if you delete the Gnd tracks between the components, and refill the zone, it would probably more act as ground plane.
Thank you for your suggestion.
I did think of that and tried it earlier but ended up getting the following error messages.
I thought the filling couldn’t get to the GND pads maybe because of not having enough space to meet the clearance criteria.
Sounds strange as there seems at least to have quite an clear area between the Pad 1 of SD1 (?) and the previous plane in the bottom right corner of your design. But maybe the clearances have large values.
Is it possible that KiCad just points out any pads not connected with ‘add tracks and vias?’ I notice that there’s filling in red under all GND components left without tracks.
(in the image below, I moved all GND pads a little bit to show the filling in red)!
Also, notice how there’s nothing under ‘Problems/Markers’ but there are a bunch of GNDs under ‘unconnected’ tab.
My expertise is probably too limited but I can’t see why the zone isn’t connected to the Pad1 of C1 (among others) and also why there are “holes” in the plane near other pads ? All those pads belong to the GND net and pad clearance shouldn’t be applied here. I probably miss something.
I think the GND zone clearance is too big.
Thank you for your response.
The only clearance criteria I know are under DRC control (Min track width, Min via size, Min uVia size)
Is this what you are referring to?
Edit the zone properties.
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