Better. However I’m wondering why you haven’t added a GND fill on the front layer, too. For example why not enlarge the GND fill below C1/C2 so that it includes the GND pad of J1? Or even fill the whole board (with a lower priority than your other fills)? Or do you plan to add other things there?
Can you post an image that has all the zones filled?
It’s very hard to see with just the hatching.
@Jonathan_Haas
Sry if I may ask some stupid questions, but I am fairly new on designing PCB’s in that way. I only have a little experience in hand soldering boards, where the most important thing is not shorting everything up.
I didn’t really think of making such a large GND fill because I don’t have a feeling of how much is enough and what may be too much.
Regarding the lower priority fill, have to figure out how that works, didn’t know there is something like that.
And no, there are no other components that I need on the board.
Here is the reworked layout with the filled zones, as @3Dogs asked for.
Much easier to see what’s going on.
Layout looks OK to me.
Layout look good to me.
If you wanted to fill the whole Front side of the board with a copper fill, you would delete your GND fill, draw a new GND fill covering your whole board (or just check the F.Cu box on your existing GND fill for the back layer to make that fill cover both layers).
If you were doing just that, you’d get issues with your GND fill overlapping your 24V and 5V fills. To avoid that, open the properties of these fills (by selecting them and pressing e) and increase their priority in that properties dialog. That will cause the GND fill to avoid these other high priority fills, similar to how it avoids pads of other nets and so on.
It’s usually always good to give touching fills different priorities, as KiCad can then figure out the clearances from your defined rules and you don’t need to draw the precise gaps manually as you did in your screenshot.
You should also stitch the same net zones on different layers together with vias. Just like the existing vias in your GND layer near the component pads, but also where there are no components, near the edges of filled areas and especially near corners. Too much doesn’t (usually?) hurt.
So, I reworked the layout with the suggested comments.
If I got it right, i “just” had to add a top gnd layer and give the existing fills a priority (with GND the highest) and add vias to the corners of the GND fill?
Looks nice.
Let us know how it works.
The latest screenshot looks nice. Now, with the fill covering the whole board, the old stitching vias are OK but less useful. The idea is to add vias in the edges of actual filled copper areas, not to the edges of KiCad zone items. You could add for example 5 vias near each board edge because the GND fills reach the edges on both sides of the board. Maybe this gives you an idea (I didn’t quickly find a more convenient way to edit the image):
Looks good, but you should/can delete the old GND fill (the one you added vias in the corners near the 24VDC IN label) as the outer GND fill contains the same area.
And after that, the via locations are obviously weird, you’d put them more on corners/edges of the GND fill and/or in a regular pattern (to ensure good connectivity). You’d also add them next to high current vias/holes of other nets, (to provide a good path for current to flow back), but you don’t really have these apart from the two test points (which probably aren’t high current) and the DC connectors (which already have a GND through-hole).
Remember that it’s good to have stitching vias close to the IC for thermal reasons.
Okay, so as @eelik suggested I removed the old vias, added the ones he draw and a couple more on the edges.
As @Jonathan_Haas suggested I deleted the old GND fill and joined it with the fill that covers the board.
This leaves the space under the IC nearly empty, is that an issue now?
Here the complete PCB
Still looks fine IMO, but note that your old smaller clearance was then below the specified clearance of your new gnd fill. If you want, you can simply lower the clearance in the zone properties.
It was better before, as long as it met minimum spacings.
You could reduce your clearances to the minimum, and try to get more copper under the IC. One thing that would help is to slide R2 closer to R1, and run the TP1 trace to R2 (BTW, this test point is kind of pointless). That would let the copper fill near C1 flow under the IC.
To be honest, at the beginning of the project, I just set the clearance settings as jlcpcb recommends for the production.
I never changed anything on them during the layout process.
Here is the screenshot of the settings (language is in german, because I speak german)
And I removed the test point, but it didn’t cover the space completely.
If you pull the VFB and 24VDC zones back to the edge of their respective pads (open up the area under the IC), the ground fills should connect.
Yes they did, thank you.
And I would like to say thank you VERY MUCH for the help and patience, to everyone here.
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