I’ve created a custom footprint and symbol for a LM66200 Dual Ideal Diode IC as I couldn’t find one in the library. Its a SOT-5X3-DRL-8.
I created the pads as I usually do, but when I place the footprint on the PCB, the ground pour doesn’t touch the ground pads? They “almost” touch, but when you zoom in there are air wires between the ground pour and the pads. I was expecting it to merge with thermal relief?
What have I done wrong !?
I compared the pad properties with other footprints I have created and they seem the same.
Yes. I have pin 4 tied to ground. Its active low, so the chip is always enabled. Pin 1, 4 and 5 should all be connected to ground, but the ground pour doesn’t seem to want to connect?
The problem is still something to do with the schematic because that is where the nets are created.
The footprints and ratlines (eventually tracks) are the physical image of the schematic.
The problem is not with the schematic or with the netlist, because KiCad is attempting to draw the thermal spokes. So it knows that the GND plane has to be connected to the three GND pads.
There is nothing wrong with the (normal) net clearance because I can see the clearance outlines around the pads. This clearance looks quite small, but on itself that is not related to the current problem.
What is weird is that the clearance between the zone and all pads from other nets (2, 3, 6, 7 and 8) is a lot bigger then to the three GND pas (1, 4 and 5).
My best guess is that you are using custom rules that do something with the clearance for the GND net. What do you get when you select both the zone, (for example) pad 6 and then: PCB Editor / Inspect / Clearance Resolution?
No, you selected two items on the same net, and my question was for two items on different nets. Experiment a bit with that function, and then try to interpret the results yourself.
I don’t know the footprint scale but if grid is 0.1mm than zone fill to go into pad 4 have to be at 0.2mm distance from pad 3 while it is not allowed to as you have set zone Clearance to 0.5.
0.5 from pad 3 looks being exactly at other border of pad 4 and zone stops there.
The clearance from the ground plane to tracks was 0.5. The ground pour for pin 4, was effectively being kept away from the trace to pin 3, by 0.5mm, which is the entire pitch of the pads, so it was disconnected from pad 4.
I have reduced the ground pour clearance to 0.2mm and now I have thermal relief connections to all pads !
A little comment on form. It is best if you don’t make connections in the form of a + it can sometimes be interpreted as two crossed wires without the connection. This happens mostly when the schematic is printed or someone makes a screenshot.
You could draw a trace from the GND pad out to the polygon fill area, or to a GND via. ( Use a lot of those, especially near signal trace transitions).
Thermal spokes are overrated. I don’t use them even on 6L boards.
Every board is an RF board, even when you don’t it to be.
