U3 Clearance Override is 0.095 mm which allows traces to the inner pads. But when trying to route the bottom right bright red pad the trace to the left becomes bright green. Same issue for the top right pad. I’m assuming it has to do with a clearance issue. What I do not know is how to handle this type of device with 0.3mm pad to pad clearance.
All help is appreciated.
I figured this out using the netclass and assigning them to the traces and pads.
The clearance around the green track overlaps with the copper of pads D3 and D4, so that is a clearance violation.
That is probably set in the footprint properties, or the pad properties. In that case, this clearance override only applies to the pads, and not to the tracks. You also have to adjust the clearance for the nets themselves. Either with the normal methods such as net classes, or write a custom rule that only applies for this footprint. You can do this with intersectsCourtyard()
Also, this would need 100um tracks and 100um clearance. Have you verified your PCB manufacturer can make this?
Let us assume the FAB house cannot. Then how would one route this device?
It would require vias to another layer. Correct? I would imagine vias would be problematic.
Some PCB fabs support via-in-pad. Typically this means a via is placed inside the pad, which is then filled and capped with copper. However, this generally costs extra as it requires extra steps during fabrication.
At this point, however, it’s clear your problem is with your choice of component and the capabilities of the PCB fabricator, not with KiCad.
There are several technologies for “via in pad”. One way is to just fill via’s with some sort of epoxy, this prevents solder paste from wicking into the via. There is also VIPPO (Via in Pad Plated Over). But this is probably prohibitively expensive if it’s needed for only this single BGA.
In your table the “minimum trace width” and “minimum spacing” of the “extended manufacturing” are compatible with what you need, but this probably also incurs an extra cost.
The best option is probably to choose another device with a bit bigger pitch.
Thanks for the information I’ll keep these layout options in mind going forward.
Also, cost isn’t a factor. This is for a project that is extremely small and this device meets the formfactor. This layout is simply to test the device before integration into the real design.
If cost isn’t a factor or is secondary to size, and you are integrating this into a larger design, you also have the option of laser vias, i.e. microvias, along with blind and buried vias. Laser vias in particular are small and will fit in even small pads. These enable tremendous flexibility.
A test board would be a good vehicle to learn about these, since there will be a learning curve. You can start here
https://www.protoexpress.com/kb/hdi-pcb-resources/
Also, here is a somewhat dated but fairly comprehensive resource:
John
