I am having a problem routing a track - it would appear that there is a large clearance rule (I assume that is what the semi-transparent area is around the track). The track is 0.25mm thick making the clearance a similar value I would guess.
In Board Setup→Design Rules→Contraints, I have set up a minimum track clearance of 0.05mm but that does not seem to affect the track routing. Are there design rules specified somewhere else that I am missing?
Andy
That is only an absolute minimum. it’s usually set to a limit that coincides with what your PCB manufacturer can make.
Yes. All nets are a member of the “Default netclass” by default. Learn how net classes work and how you can use them to your advantage.
On a sidenote. If the track you are drawing is 0.25mm wide then your via also both has a very small hole and a very narrow annular ring. If you can find a PCB manufacturer who can manufacture that, it’s probably not at a price point that you like. KiCad works at nanometer resolution, and that is very much smaller then any PCB manufacturer can make. As a result you have to make sure you use some sensible limits.
@paulvdh Thanks, net classes was the bit I was missing.
Also, the via size is within the capabilities of my PCB manufacturer (just ;-))
Andy
What minimum via annular width your manufacturer specifies?
I don’t like to work at border parameters so I always use bigger than specified minimum. But it’s just a habit I get used to.
I also don’t use 0.1mm tracks even my manufacturer accepts it.
Some manufacturers even recommend to use a bit fatter tracks and wider tolerances than their own absolute minimums to improve reliability
There’s a great tool in the “Inspect” menu called “Clearance Resolution”.
For example if I run it on this track and via, I can see all the constraints and why they do or do not apply, and what the final constraint is that is applied. The constraints checked include the global constraints you mention, plus the netclasses, plus custom design rules I’ve set.
FWIW, this looks about the same as my default: 0.25mm track, 0.3/0.5 via. It’s comfortably within JLCPCB’s capabilities, which have gotten a lot better in the last five years or so. I still don’t understand why they specify very small via annular rings, yet the “PTH annular ring” spec is ≥0.2mm. But it works.
@Heath_Raftery Yes, spot on - my design rules are based around JLCPCB capabilities. Can’t fault JLC, they keep improving their capabilities and the pricing is still better than just about any other PCB fab.
Andy
