I am finishing a PCB dual layer of big size (30cmx20cm) Almost everything is working fine. But i am trying to learn what is the reason (and solve this).
In the image is possible see 3 errors about this pad.
The firsr one: Cleareance violation required 0.250mm and actual 0.00mm
The pad is connected using a zone (Vr24) on top layer, and at bottom layer i have a zone GND.
At the eye the GND plane skip the pad without touch it.
In top layer, there are a connection from Vr24 to the pad through thermal vias. On bottom layer i see a prefect isolation with the GND
On pad propriety section (cleareance overrides) i try different values: 0.5/ 0.2 / leave blank without change on DRC error.
The zone GND has a cleareance of 0.5 with priority of 1 (i change the values and the drc ERROR still is present)
The zone Vr2 has a cleareance of 0.5 with priority of 5 (relief on PTH), I change the values and the DRC still is present.
I refill the zones, with no sucess.
The board setup has minimum cleareance of 0.2mm ( i try from 0.8 to 0 )
I have this problem on TP105 and C207, i can solve on TP, erasing the symbol on schematic, and removing from PCB, and placing again and syncing the PCB. I can do here, but i wan to learn what is happening.
In few minutes i will upload the cleareance resolution with 2 zones as described on my original post. For the moment i try replace the zone for a simple track, with same error and this report.
There are a few threads here in which “strange issues” disappear after a restart of KiCad. This is probably some kind of bug in KiCad, but the issue is too vague at the moment to make a good bug report for it. But restarting KiCad is quick and easy to try.
I have no custom rules, is basically an interconection board. Analog and digital coming from DIN41612, a lot of resistors and some OpAmp, and Outs on IDC connectors
No special rules.
Well, i update from 9.0.5 to 9.0.6 and the error was gone. Maybe some bug into 9.0.5.
