Still issues with zone fill violating DRC

I am having issues with zone fille creating DRC errors.

I looked at A September 2023 posting Issues with zone fills violating DRC
and tried Seth_h suggestion of addine ZoneConnectionFiller=1 in the kicad_advanced file. That did not change anything.

It looks like the problem was dismissed by a bunch of people in September 2023. But now it is November 2025 and the problem is still here.

Unfortunately I am still using Kicad 7 because this design was started with Kicad 7 and management does not want to switch in the middle of the design.

Application: KiCad PCB Editor x86_64 on x86_64

Version: 7.0.11-7.0.11~ubuntu22.04.1, release build

Libraries:
wxWidgets 3.2.1
FreeType 2.11.1
HarfBuzz 6.0.0
FontConfig 2.13.1
libcurl/7.81.0 OpenSSL/3.0.2 zlib/1.2.11 brotli/1.0.9 zstd/1.4.8 libidn2/2.3.2 libpsl/0.21.0 (+libidn2/2.3.2) libssh/0.9.6/openssl/zlib nghttp2/1.43.0 librtmp/2.3 OpenLDAP/2.5.19

Platform: Linux Mint 21.3, 64 bit, Little endian, wxGTK, cinnamon, x11

Build Info:
Date: Feb 21 2024 19:16:04
wxWidgets: 3.2.1 (wchar_t,wx containers) GTK+ 3.24
Boost: 1.74.0
OCC: 7.6.3
Curl: 7.88.1
ngspice: 38
Compiler: GCC 11.4.0 with C++ ABI 1016

Build settings:
KICAD_SPICE=ON

I have a very dense board. This issue is showing up on all layers with traces. It does not seem to appear on the two ground planes (this PCB has 8 layers).

If I tell the zone fill my electrical properties have a 10 mil clearance and a 10 mil Minimum Width and I tell the Board Setup Constraints Minimum clearance 7 mil and Minimum Track width 7 mils, I do not expect the Zone Generator to create DRC errors.

But it does.

Here is the situation in the first DRC warning.

Why does the Zone make a connection that is 6.75 mils wide, when I told it the minimum connection should be 10 mils? Is the “Electrical Properties Minimum Width:” in the “Copper Zone Properties” ignored when generating zones? If it cannot make a connection at 10 mils, then it should not make a connection. It should not make a connection at 6.75 mils. Am I missing something?

Hopefully this has been fixed in a later version. Has it?

Is there a suggestion as to how to fix it in version 7?

If I put a 10 mil trace there it fixes the copper connection too narrow issue, but adds another error that the track has an unconnected end. But the clearance is fine.

If I put down a copper line (not associated with a trace) it stops the zone fill and clears the error. But that does not seem like a proper fix. So how do I fix this?

Support for version 7 was stopped upon version 8 being released, with new versions released annually. In the New Year we will release version 10 - so v7 is a couple of years out of support.

Do you have a minimally reproducing test case? Can you test it with a new version (without migrating your project)? Either way, if it’s not working in v7 now, it will not be fixed.

I am not asking for it to be fixed in 7, I am looking for a work around.

And asking if it has been fixed in later versions.

I cannot believe I am the only person in the world to have this issue.

Aspects of this problem have indeed been fixed, but it is impossible to know if this exact situation has been resolved without a minimal reproducible example.

Regarding the advanced config option, if you look back at the older thread, you’ll see Seth said that the option had been added to the nightly of that time, so what is now v9 (EDIT: I missed that Seth’s reply is much later). Presumably that means there was a real issue in v7 that was at least partially resolved for v9 (presuming that connection filler config was made default on release).

I did not catch that it was that much later. Thanks. I am trying to load version 9 on my Windows 10 machine (everything else is Linux). Unfortunately I have to delete some stuff to get it to fit. So it is not happening as quickly as I had had hoped. I am hoping to not have to purchase a Windows 11 machine. My Windows 10 computer is not supported by Windows 11. The processor is too old. It will run Linux just fine.

If you can provide this we can see if it’s fixed.

The 6.75mil width is a result of the narrow gap between the two vertical tracks and further reduction for the via. There simply is not enough room to make the track wider. (At best, you can move the via a bit further to the right).

When you set PCB Editor / File / Board Setup / Design Rules / Constraints / Minimum connection width to 10 mils, that just means that copper connections that are narrower then 10 mils get flagged as DRC violations.

Also: Your via’s do not look right. The annular ring (the white part) is much to narrow, and PCB manufacturers can not make a reliable PCB with that geometry.

It is fixed in Kicad Version 9.

paulvh, there are two sets of parameters. The one you are talking about are in the design constraints. And that is 7 mils minimum clearance. And 7 mils minimum connection width. And that sets the DRC violation.

However if you look in the zone parameters There are two parameters under electrical parameters Clearance: 10 mils and Minimum width: 10 mils. If it is set like that it should never make a connection less than 10 mils in a zone. But it was in version 7. But not in version 9.

As for the via, it has a 12 mil hole diameter and a 28 mil ring outer diameter. That is 7 mils from the hole edge to the outside edge of the ring. I have not had a manufacturer complain about that. Many will go down to 5 mils from the hole edge to the outside edge of the ring, but I do not like to push it. I try to design for ease of manufacture. Not to push the edge of the manufacturer’s capability.

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In my opinion you didn’t told Zone what the minimum connection width should be, but you told it what a minimum track width it can use to fill zone. Where 10 mils track can’t go you get two tracks touching each other partially and get for example 7 mills width connection. At the same place if you allow Zone to use 8 mils track it is possible that 8 mils will be able to go there.

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