1- Used vias with 0.7 and 0.4 as the diameter and hole size
2- Used two vias per GND to have the lowest inductance
3- Used 0.3 and 0.5 track thicknesses
Do you see any issue/problem with my schematic or design, please?
PCB reviews are considered a bit “off-topic” here, and this thread will probably get closed soon. But still some remarks…
Overall this project looks quite reasonable.
To separate sections, whitespace works better then rectangles, but I do like the bigger titles above the sections.
On the PCB, the extra via’s around the circumference are not useful.
Your THT connectors are not on a 100mil grid. This makes it annoying to work with standard matrix board. It’s the same mistake as the horrible “arduino” format.
With connectors on all side, you force “addon” boards to also be so big. I quite like the blue / black pill boards, which fit in a DIP40 form factor. These can be put either on matrix board, or directly plugged into a breadboard.
The layout for the crystal and it’s capacitors is not so good. Far to long tracks for this sensitive section. It’s also become much more common to use much smaller crystals. ST has made an Application Note about crystal selection for their uc’s.
Add Silkscreen text with connector functions and pinout.
Add a production date or version / revision number.
Add a “made with KiCad” logo, and/or (company) name.
I like to have a bunch of free pads on PCB’s like this, so small circuits can be soldered directly on the development board.
STM32F103 is a pretty old and somewhat obsolete chip. It’s I/O ports works differently from newer versions, and that’s a bit annoying. I would not create a board like this myself anymore. WeAct (Aliexpress) makes quite nice and small STM32 breakout boards in DIP form factor. If you solder in the thin round pin header variant, you can put these boards into regular DIP IC sockets.
If I remember well, PORTC can handle very little current. Consider adding a transistor for the LED.
10 30pF seems a bit much for the crystal caps.
I sort of like using double via’s for connecting to the GND plane, but placing them so close together is not best practice. Especially for the uc itself, consider putting one via under the footprint, and the other on the outside. This way ground return currents will take the lowest impedance path naturally.
I suppose you have GND zone also at top layer (if not vias along borders would be no rationale).
In such case I am adding vias at least in corners of each top GND zone islands. I’m not sure of this my idea, but it is to not left floating cooper ends (being high frequency antennas) at PCB.
Imagine a coil (having inductance of L) at core. Then wound at this core a second coil with exact the same number of turns and connect them in paralel. What inductance you expect to get?
Your vias being paralel couple to each other with the effect like in these coils.
This coupling is used inside ICs having a VCC/GND pin pairs at each sides. Thanks for coupling between VCC and GND wires inside IC impedance in serie with blocking capacitors (that are connected to each such pair with as short as possible tracks - find these capacitors at my PCB) is reduced.
