I’ve been working on a web app called Netlist.io that takes a KiCad (or Altium) netlist plus any relevant datasheets and lets an LLM reason about the actual circuit. The goal is to help catch schematic issues that the usual ERC checks don’t flag, and it can also help with debugging already-fabbed boards when you describe the failure symptoms.
I started building this after too many avoidable mistakes slipped into production, and I’m hoping it can help others avoid re-spins as well. I’m looking for early users who are willing to try it out and share feedback. Would love to hear what you think!