I have a PCB with several planar coils, whre each coil is defined as a footprint composed of lines on F.Cu and B.Cu and unnamed THT pads used as vias. See the image below; each hole there is a pad acting as a via:
I tried setting the clearance override to zero or a negative number in the pad properties, but it appears to have no effect if it’s smaller than the global clearance constraint defined in the board settings. I also tried to work around this using custom DRC rules, but it appears to be impossible to selectively reduce the severity of a violation with a custom rule (it seems like it can only be increased):
I attempted a different approach where I disable the built-in clearance DRC rule and instead define my own clearance rule that conditionally ignores my coils. While working on that, I realized that I cannot actually make the DRC checker honor my rules at all. The following dummy rule is supposed to trigger a large number of errors because my board is designed with 0.1 mm clearances, but it yields nothing – DRC passes with zero errors:
The example project is working as intended, but it has a crucial difference: the default minimum clearance is set to a small value of 0.05 mm, and the custom rule uses a stricter clearance of 0.8 mm. In my case, I am trying to achieve the opposite: I need the default clearance of 0.1 mm, while allowing certain parts of the board to have collisions (clearance 0 mm). I tried disabling the built-in clearance rule, but it appears to also disable my custom rule as well:
I tried setting the board global min clearance (in the Board Setup menu) to zero, but it doesn’t work because my default net class clearance is obviously non-zero, and I don’t think it’s reasonable to change it.
I know there is an option to edit pads as geometric shapes, which allows merging the copper lines adjacent to the pad with the pad itself, but I encountered several issues here. First, each pad has copper lines on both sides of the board, and when I fuse the line on one side with the pad, the line on the opposide side for some reason disappears from the footprint; this is clearly a bug. The second issue is that I have 400 of such pads per coil, and there doesn’t seem to be a way to bulk-apply this operation to all pads. If I am missing something here, please let me know.
For now, I kinda circumvented this by temporarily deleting the coils from the PCB before running the DRC, but this is not really a workable solution. Are there any other ideas I could try?
My example was only to show that your rule from your second text really works and should be respected by the drc. It was not to solve the original question.
regarding the original question: I would try a custom rule which disables the clearance inside the coil footprints. To get more help you need to attach a small example project (maybe with one coil and a little bit of other tracks).
bulk-changing pads from normal THT to custom shaped THT is currently not supported
My own preference would be to go the other way around: Draw the tracks in such a way that no DRC violations are generated in the first place. There are at least two ways in which this can be done.
The whole “flower” construct can be drawn (scripted) in the PCB editor, and then you can also use regular vias instead of pads, and the via’s automatically adopt to the right net names.
When the whole thing is created as a footprint, then pads and and graphics on a copper layer can be combined.
Pads don’t have “names”, but they do have “numbers”. I assume you mean the pad number (Even though pad numbers can be alfa numeric strings).
I’m not sure how KiCad behaves with pads without a pad number. My first guess would be that KiCad gets confused.
Try this in the footprint editor:
Delete all spokes except one.
Delete all unconnected pads.
Give the pads that are connected to the single spoke pad number 1.
Select the pad and press [Ctrl + e] (That is “Edit pad as graphic shapes” from the context menu).
[Ctrl + e] again to exit the pad edit mode again.
Your graphic item has now become a part of the pad.
Create a circular array of this construct.
In KiCad it’s perfectly normal to have multiple pads with the same pad number in a footprint. KiCad simply assumes that all these pads have to be connected together.
You can also go for a fully scripted approach. There are several scripts for generating single inductors and for motor coils. You probably have to modify such a script quite a lot, but the general flow of drawing copper with python would be the same.
Hey Pavel, yeah that’s a tricky one. KiCad doesn’t currently allow disabling DRC just for specific areas directly. A common workaround is to define a custom net class or use zones with relaxed clearance, or temporarily suppress DRC markers after verification. Otherwise, manual exclusion is still the safest option until finer DRC control gets added in future builds.
I prepared an MWE with the coil and a few additional components. The coil footprint (and symbol) are included. It is available from here (as a new user, I cannot upload attachments): https://labfiles.zubax.com/coil_drc_mwe.zip. Schematics and a screenshot of the PCB for reference:
The coil footprint has a rule area called ROGOWSKI RULE.
Actually, originally it was made the way you described — the original coil design was drawn in a PCB editor and then converted into a footprint using a simple script based on kiutils. Since I have more than one coil in the design, and I expect to change the parameters of the coils further down the road, it is much more convenient to keep them as footprints instead of raw PCB tracks. Even if I went the PCB way, I would still have to find a way to locally reduce the clearances because the coils are made using very fine features (0.09 mm tracks/clearances, 0.15/0.3 mm vias) while the rest of the PCB uses slightly cruder features (0.1 mm tracks/vias, 0.2/0.35 mm vias), as it enables some cost cutting with my PCB manufacuturer.
Indeed, I used the word “names” precisely because they are not actual numbers
I will try constructing a new coil using fused pads as you suggested.
In the meantime you have yourself levelled up to “basic user”, so it should be possible to attach files directly in your messages. Which is preferred, because it avoids dead links (which usually happens with most external links after some time)
“Pin numbers” (or pad numbers) is pretty much a standardized term in engineering. Even for BGA’s which use “chessboard” numbers. And KiCad also calls them “numbers”. Calling them something else just leads to confusion.
There is one rather serious issue, though: with these custom rules, the interactive router becomes unusable. An attempt to drag or route a track, especially in the shove mode, causes pcbnew to hang for a minute or two for every mouse movement. Now I have to comment out the rule while working on the layout, and uncomment it when running DRC.
Is there a way to make KiCAD ignore the rule during interactive routing?
I just found another problem, more serious than the previous one: when the rules are enabled, zone fills disregard clearance settings even outside of the areas affected by the custom rules. Consider the following healthy fill where the zone clearance is set to 0.4 mm; this is outside of the coil courtyards so normal clearances apply:
When I add the custom rules, all zone fills use the default clearances of 0.1 mm, disregarding the clearance set for the zone and — most importantly — for the specific netclasses; you can see on the screenshot that the clearance of the bottom pins is violated but the DRC does not report this:
This is huge! The board has clearance violations but the DRC is green!
The problem can be reproduced with the MWE project as well, look – I defined a new netclass for nets OUT+ and OUT- with the clearance set to 0.4 mm. The ground fill violates the clearance when the rules are enabled, but the DRC passes:
This only means that my adivice was not perfect. I’m no expert in the usage of custom rules, my personal use is limited to different clearances between netclasses (high power, high voltage designs). So I use only one type of rule (copied from FAQ article: Creating a big clearance between net classes in a “High voltage” section and the rest of the PCB).
Reading the documentation again I have given you a inappropriate condition string. The function “InsideCourtYard“ returns true if the any part of the object is inside the courtyard of the given footprint. And sadly your zone is partly inside that footprint, so the condition applies also to the zone.
You could still use the condition if you enhance it and restrict the condition to items which are not from type “zone”.
You may also try (condition “A.memberOfFootprint(‘TR1’)”)), which looks also promising.
In all cases you have to read the (and experiment) with the documentation yourself. The custom rules are very powerful, but not suited for easy usage.
