I’m gradually smoothing the learning curve for schematics and simulation (thanks for the previous posts). I just spent quite some time trying to troubleshoot a simple circuit involving a D-flip/flop.
I noticed that if I leave the R or S inputs unconnected it works fine, but if I tie either of them to VCC it skuttles the flip flop and I get the dreaded unknown output (vcc/2, 1.65 or 2.5).
I’ve tried defining .param vcc=5 in the schematic. I’ve tried adding a VDC symbol at with a voltage set to {vcc}. I’ve read the section on bridging and dabbled with adc_bridge/bidi_bridge.
What’s the bare minimum I need to define to be able to tie digital inputs to VCC and have them recognized as a digital ‘high’?
This is not a simulation problem, this is a digital logic knowledge problem.
A D flip-flop has two modes of operation.
1/ Clocked: The D input state decides the output state when the Clock is applied IF the R and S are both low. Q = high if D = high when clock is applied.
2/ Direct: S = high forces Q high & R = high forces not-Q high. Both R & S high simultaneously is normally a disallowed state, however, the last to go low determines the output state.
I was assuming this truth table, taken from a 7474 chip, there was no truth table in the ngSpice manual. This table assumes inverted PRE/CLR, but I suspect the d_dff does not?
I started to get strange behavior that suggested analog signals were not being translated/bridged to digital signals for Set and Reset.
If this is unfounded and you’re certain that there is no configuration, parameters or other settings that can alter the interpretation of the voltage level of a high/low, that’s all I need, I can continue to troubleshoot my logic.
It does seem the Spice model does not have inverters on the S & R (Pre & Clr). Maybe the Name Table Port Names “set & reset” instead of “not-set & not- reset” are a hint, but I don’t know because I have still not involved myself with the Simulation section of Kicad.
I was just scratching around some ancient data books. TTL has inverters on their direct inputs but cmos does not, with respect to D ffs. I suppose the reasons are lost in the mists of time.
I think you nailed it jmk, I tried many different permutations of components, netlists and signals; hard to remember. After hours in the chair, sore neck and a headache I think it might be overlooking the ‘not’ bars. I did a quick test before quitting that showed promise.
I’m going to go over it with fresh eyes in the morning, with assumption that the analog to digital signals are working correctly. I’ll let you folk know what I found.
-John
P.S. I always learn a lot more when things go wrong; I learned a ton about KiCad and ngSpice!
What did you do to make it work? Have you made some notes along the way?
In addition, if you organize your notes a bit, and add a little writeup of the problems you encountered and how you overcame them, then it’s interesting to add it to one of the ngSpice threads with examples on this forum.
And it also helps yourself, By going another time though your notes, you will remember it better later, and you also have some organized notes for if you have forgotten details a few years in the future.
Hi Paul, I marked one of the replies as a solution, but let me try and summarize my experience from this exercise. Progress was slow due the learning curve of techniques and usage traps. I have been using version 9.0.4.
Troubleshooting
“Timestep too small; initial timepoint: cause unrecorded.” – in my mind this turns out to be almost equivalent to the old “Syntax Error” message. It covers a broad range of issues, from syntax to NetList. It is difficult to narrow down the issue, check everything (last changes, pin mappings, signal changes, etc.). Make sure all inputs are connected.
“Dot command ‘.probe alli’ and digital nodes are not compatible.” – if running a TRAN on a pure digital circuit, uncheck the “Save all currents” and “Save all power dissipations” within the analysis settings. Might be nice if somehow these are automatically ignored or grayed.
1.65V/2.5V – if an output signal of a digital device emits either of these voltages, it should be recognized as an invalid signal. This implies the circuit is not being provided proper signals to operate.
If changing the names of subckt inputs, you have to reset the component in the schematic. Occasionally I even had to restart the schematic editor. (BTW, this is called Eeschema; somehow we’re supposed to know that even though the UI does not refer to it as such.)
Debugging
Digital signals cannot be plotted, unless they’re converted to analog. Simply add a 1Meg resistor to ground to trigger the conversion. I understand this may change in future versions.
It is possible to plot signals within sub circuits (subckt). However, they first need to be converted to analog (see previous bullet) and then the following instruction needs to be inserted as a text node on the schematic canvas. Re-run the simulation to cause the signal to appear in the list.
.Save XU1.Foo.Bar – where XU1 may be the schematic symbol, Foo may be the subckt and Bar is the signal.
Design
Pay close attention to the active level of the digital signal. The “bar” or “prime” notation implies the signal is normally high, and its transition to low triggers an action. Ex: C̅L̅R̅ – this was the final issue I encountered, I was reversing the input to my flip-flop.
Null – when calling a sub-circuit, such as the d_dff, a missing argument may be represented as a ‘null’, which has the effect of declaring it as not connected.
Include a parameter to specify the VCC of a digital circuit. The analog to/from digital converters use this setting to determine the 1/0 threshold voltage.
I hit exactly the same annoying behaviour before. A couple of really small things to check that fixed it for me:
Use a real DC source for VCC (not just a label).
Put a VDC between your VCC node and GND, e.g. V1 VCC 0 DC 5 (or use a VDC part set to {vcc}) and connect the D-FF’s VCC pin to that node. If there’s no actual source tied to ground the simulator can give weird mid-rail voltages.
Make sure GND is present and correct.
If the ground reference is missing the simulator won’t know the absolute voltages and you’ll see ~VCC/2 values.
Tie inputs to the VCC node (same net) — or use a pull-up.
Connect the S or R input directly to the VCC node you created, or tie it through a small resistor (10k) as a pull-up. Floating or “soft” connections can show as undefined.
Check the flip-flop model’s supply pins.
Some symbol/models expect explicit VCC/VDD and GND pins to be hooked up. If the device’s power pins aren’t connected, the logic behaves oddly even if inputs are driven.
If the D-FF is a digital subcircuit, drive it with a digital source or compatible analog level.
Some digital models expect logic-level stimuli (logic sources) rather than ideal analog nodes. If that’s the case, use the library’s recommended VHIGH/VLOW or a pulse source that goes to 0/5V.
Quick minimal example that works:
Add V1 VCC 0 DC 5
Connect flip-flop VCC to VCC and its GND to 0
Tie S or R to VCC (or VCC → 10k → S)
Run simulation → inputs read as logic HIGH
If you still see 2.5V after that, post the exact symbol/model you’re using (and whether it has explicit power pins). Happy to look at a screenshot or netlist.
Thanks viwad, great assumptions as well, I think I side-stepped some of them because I already had a VDC source in my schematic, because it was part of a larger circuit that I’m going to make into a PCB. But the test/debugging circuits I made I omitted that; fortunately, I learned of the VCC parameter before then. But you answered an important question for me: if I have a VDC source tied to VCC, I don’t need the parameter definition.
I originally thought I had issues with tying the inputs to VCC, but realized later it was a herring.
