Hi folks,
If/when my custom model (subckt) is not behaving the way I’m expecting, what tools/techniques are available to help me debug the model?
For example, is there a way I can simply output intermediate signal values to the log? (ex: print, echo, log…)
Is there a way to assign a signal value to a different signal value (ex: q = a)
Thanks
-John
My first guess is that it’s normally done the other way around. I suspect you first create a schematic of “basic parts” that you can simulate, and when it works, you use some kind of “compiler” to create a subckt from the schematic. This does not look much like “compiling”, it’s more like netlist extraction.
I did a quick search, and the link below does mostly do this. It uses gnetlist, but I guess that Schematic Editor / File / Export / Netlist, and then use either Spice or Spice Model also does something very similar.
Also note that the link above is just the first website I looked at. Another site also guggested that a subcircuit can be created directly from a schematic. It does seem a bit silly if you’d have to number all the nodes and extract the netlist manually to create a subcircuit.
Thanks Paul, I already have the subckt created, I just need to debug it. Looking for a way to display intermediate results inside of the component. This is digital logic by the way.
Even if I were to have created the circuit first from building blocks, I can still envision a situation where I would combine it into a subckt and I would need to troubleshoot.
So, there is no way to expose points within the subckt to the simulator log window?
-John
Could you please provide a small project to allow checking the potential methods for trouble shooting?
First, I’m not very good with this ngSpice stuff, but I do have a (slightly weird) brain.
A subcircuit interacts with the rest of the schematic / simulation, so there must be a way to make nodes visible to the outside, and then you can connect “other” things to it.
Certainly.
The attached project was edited by v9.0.4 and is a test bed for creating a 74161 model.
The 74LS161A.txt is a WIP model, and the schematic intended to be wired so it will count.
Within the model I’d want visibility to things like o1, o2, o3, etc.
Thanks for your interest!
74161.zip (12.3 KB)
-John
ngspice differentiates between digital nodes and analog nodes.
In the KiCad/ngspice interface only analog nodes are visible and selectable for plotting. This is a limitation the KiCad devs should remove in the future.
Circuits with digital nodes simulate much faster than analog circuits (factor ~100).
To make digital nodes visible, you may add resistors (aka analog devices) to a node, as you have tried in your circuit for the outputs Q0 etc. Then the nodes become analog (by an internally automatically added interface). But please don’t use 1m (milli) Ohms for this purpose (output short circuited to VCC), but 1 Meg or so.
Inside the subcircuit, nodes o1 may be made visible by adding a resistor
Ro1 o1 0 1Meg.
to make node o1 analog. In addition it is necessary to tell Eeschema that there is another node by adding the command
.save xu1.xa.o1
into a text box on the Eeschema canvas. o1 is inside its subcircuit called by xa which is called by xu1. You may add
.save xu1.xb.o1
.save xu1.xc.o1
.save xu1.xd.o1
as well.
And remove U2E which is not needed. Digital nodes and devices don’t have a notion of voltage, but only low, high. and unknown.
Instead you may give the command .param vcc=5 to tell ngspice that the converted to analog nodes should carry a high voltage of 5V.
The clock pulse amplitude should be as high as the supply, e.g. 5V.
Thanks very much holger, this helps a great deal. It makes perfect sense that the NetList is ‘global’, I have to adopt more of a hardware mindset and shed decades of software development. 
…only analog nodes are visible and selectable for plotting.
…don’t use 1m
That explains so much, I’m glad you said that. It’s probably noted somewhere in the documentation, but I missed that. I actually have been using 1Meg, but I’ve added and remove the resistors so often and I didn’t realize m <> Meg.
I’ve gone ahead and added internal resistors and external .save commands and can now see the data I need to troubleshoot this - awesome!
And remove U2E which is not needed. Digital nodes and devices don’t have a notion of voltage, but only low, high. and unknown.
I have that in there for the bigger picture schematic, I’m going to be wiring this up to a PCB layout and I’m going to need to define those connections eventually. I was just taking an excerpt from a bigger diagram. But that’s good to know for simple tests.
The clock pulse amplitude should be as high as the supply, e.g. 5V.
Ok, I’ll do that, but in practice is my crystal-based oscillator going to be producing that? I was just trying to be more realistic with the voltage. Does the ngSpice need signals to be the supply voltage?
On that topic, I’m seeing some outputs ‘frozen’ at 1.65v, that sounds suspiciously specific. Does this mean I have some dependency issue, like a missing parameter or short-circuited NetList?
-John
The automatic analog-digital interface sets a threshold at VCC/2 (VCC set by .param VCC=x, x is your choice).
1.65 V is a hint to the logic ‘unknown’ output state (half of the default VCC 3.3V), after conversion from digital to analog. Something is wrong with the inputs..
I would start the design of the 74161 with a different method: Install and use symbols and models as offered by Simulation with XSPICE code models - #5 . These are indeed the digital ngspice code models, symbols with model already attached.
Use the circuit block diagram from the data sheet, duplicate it with these symbols, attach global lables to all in/out connections.
Run test simulations by providing a test input/output connected to the gobal labels
When o.k., export the ngspice netlist
Provide a subcircuit wrapper around this netlist .subckt … .ends with all node names given by the global labels, their sequence determined by the 74161 symbol pin number sequence.
Run the test again, now with the symbol/model of the 74161.
1.65 V is a hint to the logic ‘unknown’ output state (half of the default VCC 3.3V), after conversion from digital to analog. Something is wrong with the inputs..
Bingo, I think that was the final missing piece that I needed to know.
Point taken about starting from scratch, had I done that from the beginning I’d probably spent less time on it, but maybe not learned as much. Now I know a great deal about subckts, NetLists, analog/digital signals, etc. Like how to expose intermediate signals, the significance of ‘vcc’, and the mystery behind the 1.65/(now 2.5) digital signal.
This was supposed to be easy, because I was beginning with a working 74163 model and just had to make the clear asynchronous by routing the clear directly to the flip flop, instead of through gates. Then went down the rabbit hole.
I DID find that the 2.5 output was caused because 2 of my inputs were tied to vcc in the schematic (CEP/CET). Once I made those inputs go through a 1K resistor it worked. Do you have enough energy left to explain why?